Backup power circuit for biasing bit lines of a static...

Details Backup power circuit for biasing bit lines of a static... Backup power circuit for biasing bit lines of a static...

G - Physics

11

C

352/82

G11C 11/34 (2006.01) G06F 11/20 (2006.01) G11C 5/14 (2006.01) G11C 7/12 (2006.01)

Patent

CA 1166352

BACKUP POWER CIRCUIT FOR BIASING BIT LINES OF A STATIC SEMICONDUCTOR MEMORY ABSTRACT A circuit is provided for biasing the bit lines of a static semiconductor memory when each of the cells (150) within the memory is being powered by a backup power source due to failure of the primary power source. The bit lines (52) connected to the cells within the array (50) are connected to transistors (54) which bias the bit lines (52) to a high voltage upon detection of failure of the primary power for the computer. The bit lines (52) are maintained at a high voltage level to prevent discharge of a data storage node (156) through an access transistor (164) of a memory cell (150). Biasing of the bit lines (52) further prevents the integrated circuit substrate (150) from being driven excessively positive by capacitive coupling between the substrate (150) and the bit lines (52) when the primary power is restored to the circuit.

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