Backward-compatible parallel ddr bus for use in...

Details Backward-compatible parallel ddr bus for use in... Backward-compatible parallel ddr bus for use in...

G - Physics

06

F

G06F 13/40 (2006.01)

Patent

CA 2542079

A host-daughtercard interface is pin compatible with a legacy interface but redefines a subset of pins to implement a high-bandwidth double data-rate (DDR) bus. By inspecting a cookie on the daughtercard, the host platform determines whether the daughtercard supports the DDR bus or the legacy interface, and then configures the subset of pins to implement the legacy interface or the DDR bus.

Une interface hôte-carte fille comporte des broches compatibles avec une interface existante mais redéfinit un sous-ensemble de broches pour mettre en oeuvre un bus à débit de données double (DDR) et à bande passante supérieure. La vérification d'un mouchard électronique sur la carte fille permet à la plate-forme hôte de déterminer si la carte fille peut prendre en charge le bus DDR ou l'interface existante, ladite plate-forme configurant alors le sous-ensemble de broches permettant de mettre en oeuvre l'interface existante ou le bus DDR.

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