Balanced synchronous detector circuit

H - Electricity – 03 – D

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H03D 3/18 (2006.01) H04B 1/16 (2006.01)

Patent

CA 1076220

BALANCED SYNCHRONOUS DETECTOR CIRCUIT ABSTRACT OF THE DISCLOSURE A balanced synchronous detector circuit for detecting the amplitude of a received signal and for detecting the phase difference between the received signal and a gener- ated signal. A preferred application of this balanced syn- chronous detector circuit is in a stereo decoder of the type used for receiving and decoding a composite stereo signal. When so used, the balanced synchronous detector circuit receives the pilot signal normally included in the composite stereo signal and also receives locally generated signals for the purpose of generating outputs proportional to the amplitude of the received pilot signal and proportional to the phase difference between the pilot signal and the locally generated signal. These outputs can be used to control a phase-locked loop for generating the local signal and also for indicating the presence of a stereo transmission. The balanced synchronous detector circuit includes a first double-balanced modulator having a first section pro- vided with a first set of input terminals to which the re- ceived signal is applied and a second section provided with a second set of input terminals to which the locally generated signal is applied. The balanced synchronous detector circuit further includes a second double-balanced modulator having a first section formed of a portion of the second section of the first double-balanced modulator and a second section provided with a set of input terminals to which another locally gen- erated signal is applied. An output signal derived from the second section of the second double-balanced modulator is proportional to the amplitude of the received signal, and - 1 - an output signal derived from the second section of the first double-balanced modulator is proportional to the phase difference between the received signal and the locally generated signal. -ii-

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