Bank switchable memory system

Details Bank switchable memory system Bank switchable memory system

G - Physics

06

F

354/239

G06F 9/30 (2006.01) G06F 12/06 (2006.01) G11C 8/12 (2006.01)

Patent

CA 1166358

18 BANK SWITCHABLE MEMORY SYSTEM ABSTRACT OF THE DISCLOSURE A decoding circuit is coupled to the signal lines that communicate address signals to a memory unit. When a predetermined address is communicated, the decoding circuit produces a supplemental signal that is coupled to the memory unit and used to select one of a plurality of groups of memory locations. The communicated address signals specify the memory location of the selected group to be accessed.

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