H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/132
H01L 21/208 (2006.01) H01L 21/306 (2006.01) H01L 21/308 (2006.01) H01L 33/00 (2006.01) H01S 5/02 (2006.01) H01S 5/028 (2006.01)
Patent
CA 1151775
Nelson-2-1 BATCH PROCESSING OF SEMICONDUCTOR DEVICES Abstract of the Disclosure Discrete InP-InGaAsP mesa double heterostructure lasers have been fabricated by a batch process in which the laser mirrors are formed by chemically etching the wafer from the top surface down into the substrate. A feature of the process is that the metal contact on the top surface is recessed within the periphery of an overlying mask, and the etching time is controlled so that the contact is not undercut by the sidewalls of the mesa. Another feature is the use of a self limiting etchant which etches the mirrors smoothly and at a faster rate than the sidewalls. Preferably, the mirrors etch isotropically and the sidewalls etch preferentially along crystallographic planes. Also described is subsequent batch processing (e.g., forming mirror coating) and on wafer testing of the etch-mirror lasers.
371072
Nelson Ronald J.
Wright Phillip D.
Kirby Eades Gale Baker
Western Electric Company Incorporated
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