Bcd adder circuit

Details Bcd adder circuit Bcd adder circuit

G - Physics

06

F

354/198

G06F 7/50 (2006.01)

Patent

CA 1291266

ABSTRACT OF THE DISCLOSURE The BCD adder circuit for adding two BCD encoded operands and for producing a BCD encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermedi- ate sum vector and an intermediate carry vector from the sum of the operands and a precorrection factor. A second stage of the BCD adder circuit includes carry lookahead adder circuitry receiving as inputs the intermediate sum vector and the interme- diate carry vector and producing a propagate vector and a final carry vector. The third stage of the BCD adder circuit condi- tionally modifies the propagate vector to form the BCD encoded sum according to bits of the intermediate carry vector and the final carry vector as inputs.

571531

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