Bi-directional information transfer on a single direction bus

Details Bi-directional information transfer on a single direction bus Bi-directional information transfer on a single direction bus

H - Electricity

04

L

340/95

H04L 5/14 (2006.01) G06F 3/023 (2006.01) H03M 11/20 (2006.01)

Patent

CA 1158741

BC9-80-001 Abstract A central processing unit (CPU) is intercon- nected with a peripheral device such as an operator console by an interface bus of finite capacity and transfer of information is normally in a preferred direction from the CPU to the console. Provision is made to transfer other information from the console to the CPU without impacting the bus by utilizing a normally continuously operating counter in the CPU and a comparator in the console. The console comparator compares count signals from the CPU console with locally generated digital signals representative of keyboard depressions and provides a stop signal to the CPU counter over a single line when an equal compare occurs. The CPU can then interrogate the CPU counter at a convenient time and confirm a valid entry by operating indicators, such as visual and/or audible means in the console and the interface bus capacity is not impacted by the transfer of the other information from the console.

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