Biasing arrangements for electronic circuits

Details Biasing arrangements for electronic circuits Biasing arrangements for electronic circuits

H - Electricity

03

K

328/200

H03K 17/687 (2006.01) G05F 3/26 (2006.01)

Patent

CA 1154104

Abstract of the Disclosure A current mirror biasing arrangement for an electronic circuit, particularly one intended for an integrated circuit employs a current mirror constituted by series connected pnp and npn transistors having their collectors connected together. A pair of series-connected field effect transistors (FET) connected between a voltage source and ground have their gates connected to the emitter and collector of the pnp transistor and their junction to the pnp transistor gate. The pnp transis- tors to be biased have their gates connected to the said FET junction, The gate current of the operative FET can be made negligible so that substantially perfect matching is obtained between the npn transistor current and the "mirror': biasing current. Preferably the FET are of subsurface junction type, their low pinch-off voltage and low gate current making them particularly suitable for low voltage application. , .

362481

Affiliated with

Also associated with

Rating

Biasing arrangements for electronic circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Biasing arrangements for electronic circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Biasing arrangements for electronic circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-540987