Bicmos ecl-to-cmos level translator and buffer

Details Bicmos ecl-to-cmos level translator and buffer Bicmos ecl-to-cmos level translator and buffer

H - Electricity

03

K

H03K 19/0175 (2006.01) H03K 19/003 (2006.01) H03K 19/013 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 2141058

An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The cur- rent mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capa- bility. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers re- sults in improved high-to-low transition times.

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