Bicmos logic circuit

Details Bicmos logic circuit Bicmos logic circuit

H - Electricity

03

K

H03K 19/082 (2006.01) H03K 17/14 (2006.01) H03K 17/567 (2006.01) H03K 17/60 (2006.01) H03K 19/086 (2006.01) H03K 19/0944 (2006.01) H03K 19/0948 (2006.01)

Patent

CA 2127474

2127474 9317498 PCTABS00025 An improved BiCMOS logic circuit (70) utilizes an emitter-coupled pair of bipolar transistors (21, 22) for differentially comparing an input signal (Vin) with a logic reference level (VBIAS). Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors (26, 27) coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal (VREF2) providing a variable load resistance. The control signal is preferably provided by a feedback network (52, 53) which maintains a constant voltage swing across the network over temperature.

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