Bicmos output buffer noise reduction circuit

Details Bicmos output buffer noise reduction circuit Bicmos output buffer noise reduction circuit

H - Electricity

03

K

H03K 19/0175 (2006.01) H03K 19/00 (2006.01) H03K 19/003 (2006.01) H03K 19/0944 (2006.01)

Patent

CA 2084602

Attorney Docket No. NS18692 BICMOS OUTPUT BUFFER NOISE REDUCTION CIRCUIT Abstract A BICMOS output buffer circuit delivers output signals of high and low potential levels at an output (VOUT) in response to data signals at an input (VIN). A CMOS output pulldown driver transistor (Q60) sources base drive current to a relatively large current conducting bipolar primary output pulldown transistor (Q44). A relatively small current conducting CMOS secondary output pulldown transistor (Q60A) is coupled with primary current path in parallel with the primary current path of the bipolar primary output pulldown transistor (Q44) between the output (VOUT) and low potential power rail (GNDN). The control gate node of CMOS secondary output pulldown transistor (Q60A) is coupled to the control gate node of the CMOS output pulldown driver transistor (Q60) to initiate pulldown of a small sinking current before turn on of the bipolar primary output pulldown transistor (Q44) to reduce the maximum peak output noise (VOLP). A feed forward circuit capacitance is coupled between the control gate node of the CMOS output pulldown driver transistor (Q60) and base node of the bipolar output pulldown transistor (Q44). The capacitance value is selected to pass a transient capacitive current sufficient for early turn on of the bipolar output pulldown transistor before the CMOS output pulldown driver transistor delivers sustained conduction current to reduce the maximum "valley" output noise (VOLV).

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