Bidirectional data byte aligner

Details Bidirectional data byte aligner Bidirectional data byte aligner

G - Physics

06

F

354/237

G06F 13/16 (2006.01) G06F 12/04 (2006.01)

Patent

CA 1205207

BIDIRECTIONAL DATA BYTE ALIGNER Abstract A byte-addressable memory system having an array of transceivers with control logic which enables memory to be addressable on individual byte boundaries rather than on two byte (word) or four byte (longword) boundaries. The memory system has two independent even-address and odd- address segments allowing parallel access to two longwords (eight bytes or one quadword) simultaneously. Logic determines which of the eight bytes should be placed on a four byte bus and the sequential order of the bytes on the bus. The entire operation takes place in one memory cycle time period and can start at any byte address.

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