Bifurcate buffer

Details Bifurcate buffer Bifurcate buffer

H - Electricity

03

M

H03M 9/00 (2006.01) G06F 5/10 (2006.01) H04L 29/02 (2006.01) H04Q 3/52 (2006.01) G06F 13/38 (2006.01)

Patent

CA 2615649

A buffer includes a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, a plurality n of buffers and a media access controller having inputs coupled to the plurality of de-serializers, data outputs coupled to the buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-nth that of the input data. Preferably the buffer is a bifurcate buffer. In operation, serial packets are received on a port. They must be converted to parallel data for processing by conventional CMOS logic, however there are limits serial to parallel conversion ratio. This buffer describe circumvents theses limits.

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