Binary divider with carry-save adders

Details Binary divider with carry-save adders Binary divider with carry-save adders

G - Physics

06

F

354/182

G06F 7/52 (2006.01)

Patent

CA 1142650

Abstract of the Disclosure A high-speed binary divider is provided which produces two quotient bits per processor cycle using two carry-save adders in a nonrestoring division mode with a delayed sign logic circuit selecting the adder having the required adder result for the current partial remainder.

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