Binary floating point arithmetic rounding in conformance...

Details Binary floating point arithmetic rounding in conformance... Binary floating point arithmetic rounding in conformance...

G - Physics

06

F

G06F 7/38 (2006.01) G06F 7/52 (2006.01) G06F 7/552 (2006.01)

Patent

CA 2045662

2045662 9110189 PCTABS00006 A method and a high speed processor (HSP) incorporating that method are set forth for processing signals representing outputs generated by remainderless division algorithms (102) and remainderless square root algorithms so as to obtain rounded outputs (112) conforming to the IEEE 754-1985 binary floating point arithmetic standard. The method and procedure of the present invention allow the solutions of floating-point computations to be rounded such that sign bits, as well as binary bits, of the rounded results are in full compliance with all guidelines of the stated standard.

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