Binary multiplier circuit including coding circuit

Details Binary multiplier circuit including coding circuit Binary multiplier circuit including coding circuit

G - Physics

06

F

354/182

G06F 7/52 (2006.01) G06F 7/49 (2006.01) H03M 7/00 (2006.01)

Patent

CA 1089569

BINARY MULTIPLIER CIRCUIT INCLUDING CODING CIRCUIT Abstract of the Disclosure A binary multiplier circuit wherein the product is expressed in coded form as soon as the linear (or non-coded) product is produced. When a twelve-bit binary number is multiplied by another twelve-bit binary number a twenty-four bit binary number is produced. The twenty-four bit product can be coded as an unsigned seven-bit binary number (µ-255 code) as follows. The number 33 x 211 in binary form is added to the linear product to form an augmented product. The number of leading zeroes in the augmented product is counted and the base-minus-one complement of the count is used for the three most significant bit positions of the coded product. The four next most significant bits of the augmented product, after the most significant logic 1, are used for the four least significant bit positions of the coded product. Suitable circuitry is described which allows the coding process, just described, to take place while the linear product is in the process of being formed, and produces the coded result when the final linear product is completed. - i -

301370

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