Bipolar field-effect electrically erasable programmable read...

G - Physics – 11 – C

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G11C 16/02 (2006.01) H01L 21/28 (2006.01) H01L 21/336 (2006.01) H01L 21/8249 (2006.01) H01L 27/105 (2006.01) H01L 27/115 (2006.01) H01L 29/788 (2006.01)

Patent

CA 1327646

A BIPOLAR FIELD-EFFECT ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY CELL AND METHOD OF MANUFACTURE ABSTRACT OF THE DISCLOSURE A floating gate electrically erasable MOS transistor comprising a silicon substrate having source and drain regions and a channel region disposed between the source region and the drain region. The source and drain regions are formed from a semiconductor material having one conductivity type, and the channel region is formed from a semiconductor material having a conduc- tivity type opposite the conductivity type of the semi- conductor material forming the source and drain regions. A control gate region is formed in the silicon substrate horizontally spaced apart from the channel region. The gate region is formed from a semiconductor material having the same conductivity type as the semiconductor material forming the source and drain regions. A poly- silicon layer bridges the control gate region and the channel region for communicating an electrical potential from the first gate region to the channel region. A silicon dioxide layer is disposed between the polysilicon layer and the control gate and channel regions for in- sulating the polysilicon layer from these regions. The polysilicon layer thus serves the function of a floating gate, and is selectively controlled through the first gate region for forming a conductive channel between the source and drain regions. The drain region of the MOS transistor is coupled to the base terminal of a bipolar sensing transistor for forming an EEPROM.

607549

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