Bist memory test system

Details Bist memory test system Bist memory test system

G - Physics

11

C

G11C 29/00 (2006.01) G11C 29/08 (2006.01) G11C 29/14 (2006.01) G11C 29/50 (2006.01)

Patent

CA 2212089

A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.

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