G - Physics – 08 – C
Patent
G - Physics
08
C
354/222
G08C 25/00 (2006.01) H04L 1/24 (2006.01)
Patent
CA 1105144
ABSTRACT A bit error detecting circuit for detecting errors in digital sig- nal transmissions is disclosed. An input digital signal is fed to a clock recovery circuit which reproduces a clock signal to clock first and second decision circuits and a digital pattern generator. The input digital signal is fed to the first decision circuit which produces a decision output based on a first reference level. The input digital signal is also added to a predetermined binary code pattern produced by the pattern generator and the combined signal is fed to the second decision circuit which produces a deci- sion output based on a second reference level. The two decision outputs are fed to respective inputs of an Exclusive-OR circuit. The use of the pattern generating circuit contributes to very stable operation which can be further improved by incorporating a capacitor in the circuitry for adding the input signal and the predetermined signal.
309233
Nippon Electric Co. Ltd.
Smart & Biggar
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