Bit error detection circuit for psk-modulated carrier wave

H - Electricity – 04 – L

Patent

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Details

325/80, 363/10.1

H04L 1/24 (2006.01) H04L 27/22 (2006.01) H04L 27/227 (2006.01)

Patent

CA 1231388

ABSTRACT A bit error detecting circuit for a PSK-modulated carrier wave is described. It includes a first demodulator responsive to a reference carrier wave for phase-demodulating an input PSK carrier wave into a first demodulated signal. Also included is a carrier wave recovery circuit for providing the reference carrier wave in response to the input PSK modulated carrier wave or the first demodulated signal. A clock signal recovery circuit provides a clock signal in response to the input PSK modulated carrier wave or the first demodulated signal. A modulator phase-modulates the reference carrier wave with the output of an oscillator. A second demodulator is responsive to the output of said modulator means for phase-demodulating the input PSK modulated carrier wave into a second demodulated signal. A first discriminator dis- criminates the first demodulated signal into a first digital signal in response to the clock signal, and a second discriminator discriminates the second demodulated signal into a second digital signal in response to the clock signal. A comparator compares the first digital signal with the second digital signal to provide a bit error detection signal. The circuit of the invention is capable of predicting in a stable manner a bit error rate on a transmission line even when the operating point of a non-linear element on the transmission line fluctuates.

452082

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