G - Physics – 06 – F
Patent
G - Physics
06
F
354/222, 354/57
G06F 11/00 (2006.01) G06F 7/02 (2006.01) H04L 1/00 (2006.01)
Patent
CA 1203912
Abstract of the Disclosure In a bit pattern check circuit, there are provided three memory devices and a bit pattern input is divided into portions of the number same as that of the memory devices. One portion of the divided bit pattern input is stored in the first memory device. The second and third memory devices are inputted with the other portions of the divided bit pattern and outputs of preceding memory devices respectively. The content of the third or last stage memory device is outputted through an OR gate circuit. This bit pattern check circuit has a simple construction but can accurately check a plurality of bit patterns each comprising a plurality of bits.
444240
Corporation Nec
Smart & Biggar
LandOfFree
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