Bit serial convolutional decoder for vlsi implementation

Details Bit serial convolutional decoder for vlsi implementation Bit serial convolutional decoder for vlsi implementation

H - Electricity

03

M

354/67, 354/223.

H03M 9/00 (2006.01) G06F 11/18 (2006.01) H03M 13/41 (2006.01)

Patent

CA 1210513

27284-3? ABSTRACT A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate ?,constraint length 7 code with generator polynomials x6+x5+ x3+x2+1, and x6+x3+x2+x+1. The architecture of the instant decoder is appropriate for implementation on a single monolithic VLSI integrated circuit chip and includes a branch metric calculator circuit which produces output signals representative of input sym- bol signals. These output signals are supplied to a metric update circuit which evaluates the signals from the calculator circuit and provides decisions to a path update circuit which converges the signals thereto and the output signals of which are evaluated by a majority vote circuit which produces data output signals repre- sentative of data input signals.

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