Bit-serial integrator circuitry

Details Bit-serial integrator circuitry Bit-serial integrator circuitry

G - Physics

06

F

354/153

G06F 7/48 (2006.01) G06F 7/50 (2006.01)

Patent

CA 1290458

ABSTRACT A bit-serial integrator includes the cascade combination of a bit-serial adder, a first bit-serial register and a second bit-serial register. Input signal is applied to one input of the adder and the output terminal of the second bit-serial register is coupled to a second input of the adder. A transparent latch is coupled to an output of the first bit-serial register and is conditioned to pass a predetermined number of sample bits and then to latch and output a particular sample bit for the duration of a sample period. The output of the latch is an integrated, scaled and truncated representation of the input signal.

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