Block normalization processor

Details Block normalization processor Block normalization processor

G - Physics

10

L

G10L 19/02 (2006.01)

Patent

CA 2520127

A method and apparatus for implementing a vocoder in an application specific integrated circuit (ASIC) is disclosed. The apparatus contains a DSP core (4) that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further comprises a specifically designed slave processor to the DSP core (4) referred to as the minimization processor (6). The apparatus further comprises a specifically designed block normalization circuitry.

La présente invention concerne une méthode et un appareil pour la mise en oeuvre d'un vocodeur dans un circuit intégré spécifique. L'appareil contient un noyau de traitement numérique de signaux (DSP) (4) qui exécute des calculs selon une architecture à jeu d'instructions réduit (RISC). Le circuit comprend aussi un processeur asservi spécifiquement conçu pour le noyau DSP (4) et appelé le processeur de minimisation (6). L'appareil comprend également un circuit de normalisation de blocs spécifiquement conçu.

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