Block redundancy for memory array

Details Block redundancy for memory array Block redundancy for memory array

G - Physics

06

F

354/224

G06F 11/16 (2006.01) G11C 29/00 (2006.01)

Patent

CA 1163374

14 ABSTRACT OF THE DISCLOSURE Block redundancy is utilized to improve yield and lower die cost for an electrically programmable read only memory (EPROM). The EPROM is organized 8Kx8 with four primary memory blocks (12A,12B,12C,12D) on each side of a central row decoder. Each block includes an array (M) of memory cells, column select (CS), column decode (CD), sense amp (SA), data buffer (DB) and other overhead circuitry. One block of redundant circuitry (12RB-1) is also provided for each set of four blocks and includes a redundant memory matrix (RM), a redundant column decoder (RCD), a redundant column select (RCS), a redundant sense amp (RSA) and a redundant data buffer (RDB). Incorporated within each primary memory block is a multiplex logic circuit (MUX) which is independently programmable to selectively disconnect the associated primary memory block and substitute the redundant memory block, including the redundant column decoder, column select, sense amp and data buffer. Each multiplex logic circuit (26) includes a polysilicon fuse (30) which is permanently programmable from a closed to an open circuit condition by applying a high voltage to the external data bit terminal (P1)which corresponds with the defective memory block bells.

370650

Affiliated with

Also associated with

Rating

Block redundancy for memory array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Block redundancy for memory array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Block redundancy for memory array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-477144