Boolean processor case

G - Physics – 06 – F

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354/230.3, 354/2

G06F 9/30 (2006.01) G05B 19/05 (2006.01) G06F 9/305 (2006.01) G06F 9/38 (2006.01) F02B 75/02 (2006.01)

Patent

CA 1234223

PROGRAMMABLE CONTROLLER ("PC") WITH IMPROVED BOOLEAN PROCESSOR ABSTRACT OF THE DISCLOSURE A very fast and efficient Boolean processor ("BP") (20) capable of compiling a full range of diagrams or expressions in ladder, logigram, and Boolean with a small but powerful instruction set. The BP includes an instruction decoder (34), combinatoric logic (35), a T-register (42) which holds the temporary results of a sequential AND operation, an N-register (43) which holds the initial Boolean value of T, a Binary Accumulator Memory ("BAM") (40) which is used as a scratchpad for a program which evaluates a ladder or logigram diagram or a Boolean expression, a source address ("S") in BAM (40) from which an initial operand is taken, a destina- tion address ("D") in BAM (40) in which the result of an operation is stored, and a destination address regis- ter ("DAR") (45) in which the destination address is stored. The instruction set includes a subset of input instructions and a subset of structure instructions. The operand (I) of an input instruction is an address in IOIM (25). The operands (S,D) of a structure in- struction are source and destination addresses in BAM (40). Each input instruction reads the value of a bit from IOIM and has the effect of logically combining this bit value with the value held in the T-register and possibly with the destination bit in BAM. The struc- ture instructions cause operation on the pair of ad- dresses S and D, and either describe the structure of the diagram to be compiled or permit the performance of logical functions between nodes in the diagram.

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