Bootstrap driver circuits for an mos memory

G - Physics – 11 – C

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G11C 11/34 (2006.01) G11C 7/12 (2006.01) G11C 8/08 (2006.01) H03K 5/02 (2006.01) H03K 19/017 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 1166745

BOOTSTRAP DRIVER CIRCUITS FOR AN MOS MEMORY ABSTRACT OF THE DISCLOSURE: A high speed, low power bootstrap driver is disclosed for use in an MOS memory. The basic driver includes first and second enhancement mode transistors for receiving a digital input. The drain of the first transistor is coupled to a high impedance depletion mode transistor, and the drain of the latter transistor is coupled to the source of a low impedance transistor. Another enhancement mode transistor is coupled via its sources to the drain of the second enhancement mode tran- sistor and is coupled via its gate to the drain of the first enhancement mode transistor. A capacitor is con- nected between the drain of the high impedance transistor and the drain of the second enhancement mode transistor. When a low level input is received, the drain of the first enhancement mode transistors is rapidly boot- strapped to a high level voltage above the positive power supply for use as an output signal. A key modi- fication to the driver described above adapts the driver for use in a fully asynchronous environment. Further modifications to the basic driver are described for use of the driver in a decoder, a buffer, and a clock generator.

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