Boundary scan method for terminating or modifying integrated...

Details Boundary scan method for terminating or modifying integrated... Boundary scan method for terminating or modifying integrated...

G - Physics

01

R

G01R 31/28 (2006.01) G01R 31/3185 (2006.01)

Patent

CA 2347846

A JTAG Boundary Scan method by which the on-chip system logic (OCSL) of an integrated circuit is changed by use of a state machine which, among other functions, allows a predefined set of instructions (80, 89) to be loaded into an Instruction Register and then executed. The predefined instructions (80, 89) are designed to follow in sequence after certain other previous instructions. The instructions (80, 89) change the OCSL from one state to another state and allows the state to be changed without the need of a full device reset. Additional instructions within this invention were created to have attendant operating modes for which termination is self timed within the integrated circuit. Additional instructions further control the implementation of instruction execution within the state machine.

Cette invention concerne un procédé de balayage de front JTAG permettant de modifier la logique système sur puce (OCSL) d'un circuit intégré à l'aide d'une machine finie qui, entre autres fonctions, permet de charger un ensemble prédéterminé d'instructions (80, 89) dans un registre d'instructions et de les exécuter. Les instructions prédéterminées (80, 89) sont conçues de manière à suivre séquentiellement certaines autres instructions préalables. Les instructions (80, 89) font passer l'OCSL d'un état à un autre, et permettent de changer d'état sans qu'il soit nécessaire d'effectuer une remise à zéro complète du dispositif. Cette invention concerne également des instructions complémentaires qui possèdent des modes de fonctionnement concomitants pour lesquels l'arrêt est auto-programmé dans le circuit intégré. D'autres instructions permettent en outre de commander la mise en oeuvre de l'exécution des instructions dans la machine finie.

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