G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 12/02 (2006.01) G06F 13/28 (2006.01) G06F 13/40 (2006.01) G06F 12/06 (2006.01)
Patent
CA 2160499
A computer system that has two buses with different memory addressing capacitiesand a first bus master that generates M-bit addresses is provided with a bridge between the two buses. In order to generate N-bit addresses for use on the second bus, a direct memory access (DMA) controller on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus to address memory. The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.
Bland Patrick Maurice
Cronin Daniel R. III
Hofmann Richard G.
Moeller Dennis
Venarchick Lance M.
International Business Machines Corporation
Rosen Arnold
LandOfFree
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