Buffer address register

Details Buffer address register Buffer address register

G - Physics

06

F

354/246

G06F 5/06 (2006.01) G06F 7/78 (2006.01)

Patent

CA 1293333

ABSTRACT A buffer address register is disclosed having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the addresses already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be retransferred to the buffer address register for read out.

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