Buffer memory circuit arrangement capable of receiving a...

Details Buffer memory circuit arrangement capable of receiving a... Buffer memory circuit arrangement capable of receiving a...

G - Physics

06

F

354/238

G06F 12/08 (2006.01)

Patent

CA 1300759

Abstract of the Disclosure; In a buffer memory circuit arrangement which receives a previous request given from a request source together with a previous address and which is loaded with a block of data units by block transfer from a main memory in the absence of the block, an avail control circuit (21) and a request control circuit (22) receive a following request along with a following address even in the course of the block transfer, regardless of the following address. The following request can be processed within time intervals between write intervals which are defined during the block transfer to write the data units into a buffer memory (16, 17). After the following request is processed, an additional request can also be received before completion of the block transfer by monitoring, in a restart controller (41), the previous and the following addresses and the number of memory reply signals sent from the main memory during the block transfer.

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