Buffer memory control apparatus

Details Buffer memory control apparatus Buffer memory control apparatus

G - Physics

06

F

354/239

G06F 12/08 (2006.01) G06F 12/10 (2006.01)

Patent

CA 1304827

ABSTRACT OF THE DISCLOSURE For address identification of a cache memory, a part of address bits of a logical address which are subject to address translation through a TLB and a part of address bits of the logical address which are not subject to address translation are applied in combination to an address array of the cache memory. Synonym generation is detected in response to buffer miss and synonym invalidation is executed in the buffer address array.

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