Buffer memory control circuit for label scanning system

Details Buffer memory control circuit for label scanning system Buffer memory control circuit for label scanning system

G - Physics

06

K

354/56

G06K 9/62 (2006.01) G06K 7/016 (2006.01) G06K 7/10 (2006.01)

Patent

CA 1148259

BUFFER MEMORY CONTROL CIRCUIT FOR LABEL SCANNING SYSTEM Abstract A scanning system includes a pair of buffer memories for alternately accumulating strings of signals which may contain bar coded label data. Candidate selection logic circuits examine incoming signals to generate a candidate signal when a string of signals satisfies gross logical tests. A control counter responds to the incoming sig- nals and to the candidate signal to select an alternate buffer memory only when the active memory is fully loaded and contains at least part of a label candidate. The contents of the fully loaded memory are transferred to a processor for further analysis while incoming signals are routed to the alternate memory.

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