Burst address sequence generator

Details Burst address sequence generator Burst address sequence generator

G - Physics

06

F

G06F 12/06 (2006.01) G06F 12/02 (2006.01)

Patent

CA 2045224

11 ABSTRACT A kind of burst address sequence generator (10) is to generate 2n pulse trains (n is an integer greater than l) compatible with INTEL 80486 CPU, including the following: One n-bit binary up counter (11), whose input terminal inputs a signal of one first pulse train address (ZERO#) for initializing and to begin counting, and an increment signal (INC) used to trigger the input. The output terminal has n count signal C(0, ..., n-1) to couple to n corresponding XOR gates (12): one transparent latch (13), whose input terminal inputs n address bit A(m, ..., m+n-1) signals (in other words, 2n pulse train burst cycles with size of each transmission data at 2m bytes; A0~A(M-1) as the continuous lowest address of this 2m bytes); one of the input signals and one latched act signal (ALE), the output is the n latched address signals LA(m, ..., m+n-1), as well as n corresponding XOR gates coupled with the n count signals C(O, ..., n-1) and n latched address signals LA in order to obtain n pulse train address signals SA(m, ..., m+n-1). SA can be directly coupled to a static random access memory (SRAM). This invention also concerns a pulse train burst address sequence generator (20), with a delay reduction function to reduce the delay time of address generation by the above-mentioned pulse train burst address sequence generation.

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