Burst gate circuit

Details Burst gate circuit Burst gate circuit

H - Electricity

04

N

350/71

H04N 9/455 (2006.01)

Patent

CA 1112755

Abstract A burst gate pulse generating circuit includes a normally saturated transistor (60) responsive to a pulse (Vs) representative of a horizontal sync component of a video signal which includes a burst interval. The sync pulse is coupled to a base input of the transistor via an RC differentiating network (52, 56, 58) for causing the transistor to operate between saturated and cut-off states, such that a gate pulse (Vo) produced at the transistor collector output is delayed relative to the sync pulse and substantially coincides with the burst interval. The circuit is arranged so that the sync pulse as coupled via the differentiating network (52, 56, 58) causes the base-emitter junction of the transistor to break down in the reverse direction. The timing of the output gate pulse is therefore substantially independent of they sync pulse amplitude, which can vary undesirably, thereby promoting accurate pulse timing.

328043

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