Burst read address generation

Details Burst read address generation Burst read address generation

G - Physics

06

F

G06F 13/28 (2006.01) G06F 12/02 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2079564

ABSTRACT OF THE DISCLOSURE A memory system couples to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes means for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of the set of address sequences as a function of the states of these bits. A first predetermined address bit is used to select different sequences of addressed readout data words to be transferred by the pair of DRAMs to the user. A second predetermined address bit is complemented to reverse the two high order address responses with the two low order address responses of specific address sequences. These operations are utilized to all of the required address sequences within the different subgroups.

Affiliated with

Also associated with

Rating

Burst read address generation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Burst read address generation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Burst read address generation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1364580