Bus clock extending memory controller

Details Bus clock extending memory controller Bus clock extending memory controller

G - Physics

06

F

354/231

G06F 1/12 (2006.01) G06F 13/42 (2006.01)

Patent

CA 2028552

BUS CLOCK EXTENDING MEMORY CONTROLLER Abstract of the Disclosure A memory controller provides a stretch signal to a bus controller which develops the synchronizing signal used on a synchronized bus, alleviating the need to insert a full wait state during memory read operations. The memory is located off a second bus which is tightly coupled to the processor, but devices operating according to the protocol of the synchronized bus can access the memory. The memory controller controls the buffers and address multiplexing between the second bus and the memory devices, while the bus controller controls the buffering and latching between the first and second buses. The memory controller also develops the row and column address strobes used by the memory devices.

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