Bus executed scan testing method and apparatus

Details Bus executed scan testing method and apparatus Bus executed scan testing method and apparatus

G - Physics

01

R

356/117

G01R 31/3185 (2006.01) G06F 11/27 (2006.01)

Patent

CA 1296109

BUS EXECUTED SCAN TESTING METHOD AND APPARATUS Abstract of the Disclosure For LSI/VLSI integrated circuits which inherently have an address decoder and a data bus, an scan testing method and apparatus is presented which does not require additional pin connections to be dedicated for scan test implementation. Counter to the Joint Test Action Group approach, the present invention uses additional registers, multiplexers, and decoders in conjunction with the existing buses to provide test access to otherwise embedded layers of logic circuitry, without the addition of a single pin connection to a integrated circuit chip package. Further, since this test method and apparatus uses the data bus and registers just as the rest of the chip, slow and complex d.c. level shifting equipment is not required.

611045

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