Bus locking fifo multi-processor communication system

Details Bus locking fifo multi-processor communication system Bus locking fifo multi-processor communication system

G - Physics

06

F

G06F 13/38 (2006.01) G06F 13/42 (2006.01) G06F 15/16 (2006.01)

Patent

CA 2074530

2074530 9111768 PCTABS00006 A message transfer system for transferring message data from a master processor (1140) across a VMEbus (22) to a slave processor (1140). The message transfer system includes a FIFO (1120) interconnected to the VMEbus (22) for receiving and storing the message data transferred from the master processor (1140). The FIFO FULL state, which indicates that FIFO (1120) is unable to store message data, and generates a FIFO FULL signal (1125) to indicate the existence of the FIFO FULL state. The system further includes a means (1130) interconnected to the FIFO (1120) and the VMEbus (22) responsive to the receipt of a FIFO FULL signal (1125) from the FIFO (1125).

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