Bus master arbitration circuitry having improved prioritization

Details Bus master arbitration circuitry having improved prioritization Bus master arbitration circuitry having improved prioritization

G - Physics

06

F

G06F 13/20 (2006.01) G06F 13/364 (2006.01)

Patent

CA 2140685

An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

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