Bus monitor system

Details Bus monitor system Bus monitor system

G - Physics

06

F

G06F 13/378 (2006.01) G06F 11/34 (2006.01)

Patent

CA 2187051

BUS MONITOR SYSTEM A bus monitor system comprises eight identical pro- grammable monitor circuits that are each connected to a monitored bus and to a local 16-bit event bus. There are three interfaces to they event bus within each monitor circuit. one interface asserts a predetermined bit pat- tern on the event bus when match conditions occur between bit patterns on the monitored bus and predetermined bit patterns stored in monitor circuit registers. A second interface asserts a signal on an external pin when bit patterns on the event bus match a predetermined bit pat- tern stored in a monitor circuit register. A third inter- face asserts a predetermined bit pattern on the event bus when an external device has asserted a signal on an ex- ternal pin. Each monitor circuit is capable of reading and asserting any of the bits of the event bus. The event bus is used to enable or disable monitor circuit inter- faces. If any asserted bit on the event bus matches a corresponding bit of one of the predetermined bit pat- terns stored in the interface enable and disable regis- ters, that interface will be enabled or disabled, respec- tively. The event bus gives the monitor system the abil- ity to simultaneously monitor for multiple bit patterns on the monitored bus, and to monitor for a sequence of bit patterns by halving one monitor circuit trigger another.

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