Busy indicating arrangement for bus in a data processing system

Details Busy indicating arrangement for bus in a data processing system Busy indicating arrangement for bus in a data processing system

G - Physics

06

F

354/231, 340/92

G06F 13/00 (2006.01) G06F 13/374 (2006.01) G06F 13/42 (2006.01)

Patent

CA 1143853

ABSTRACT OF THE DISCLOSURE A data processing system including a plurality of data devices, an interconnection and clocking circuitry. When one of the data devices is to transfer information to a second data device over the interconnection cir- cuitry, it generates a first signal onto the interconnection circuitry for a predetermined number of clock pulses. The second data device then generates the first signal after the predetermined number of clock pulses to the end of the transfer.

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