H - Electricity – 04 – J
Patent
H - Electricity
04
J
H04J 3/16 (2006.01) H04B 10/20 (2006.01) H04L 12/56 (2006.01) H04L 29/06 (2006.01)
Patent
CA 2154716
A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a first-in-first-out (FIFO) buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. Achannel module, which is disposed between a switch module and a plurality of fiber optic channels, comprises a port intelligence system and a memory interface system. The port intelligence system is responsible for transmitting and receiving data from the fiber optic channels in accordance with a predetermined protocol, preferably Fibre Channel. The memory interface system comprises a receive memory unit, a transmit memory unit and memory control logic. When an intermix frame is to be passed through the switch, the intermix frame is passed to a FIFO concurrently while class 1 data transfer occurs via the bypass bus. After the intermix frame has been completely written into the FIFO, the memory control logic waits to detect a tagindicative of a break in the class 1 data transfer. The control logic will then switch the MUX and cause the FIFO to commence writing the intermix frame to the port intelligence system for transfer to a predetermined fiber optic channel.
Bennett Dwayne R.
Wu Wayne
Yeung Clifford S.
Hewlett-Packard Company
Sim & Mcburney
LandOfFree
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