G - Physics – 11 – C
Patent
G - Physics
11
C
354/241
G11C 7/00 (2006.01) G06F 9/30 (2006.01) G06F 9/38 (2006.01) G11C 7/10 (2006.01) G11C 8/12 (2006.01)
Patent
CA 1183275
BYTE ADDRESSABLE MEMORY FOR VARIABLE LENGTH INSTRUCTIONS AND DATA Abstract A random access memory having the capability to access one or more bytes in one or more memory word locations of a multi-byte memory array within one memory cycle. Variable length instruction and data words composed of multiple bytes are stored in a block of addressable locations in a memory so that individual bytes of each word are aligned in columns. Each column of bytes is addressable independently of the other byte columns via adders. A most significant bit portion of a memory location address is fed into a first input of column adders and the output of a first decoder circuit is fed into a second input of the adders for address incrementing within one memory cycle. A second decoder circuit generates a separate read or write enable line to each column of bytes. Both decoders are controlled by a least significant bit portion of the memory address and reference word byte size codes. A bi-directional multiplexer rearranges the order of the bytes so they appear in the proper order at the memory interface.
411468
Edry Richard J.
Howes H. Frank
Schwartz Martin J.
Raytheon Company
Smart & Biggar
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