G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 15/78 (2006.01) B61L 3/12 (2006.01) B61L 3/22 (2006.01) B61L 3/24 (2006.01) G05B 19/05 (2006.01) H03K 19/177 (2006.01)
Patent
CA 2625157
A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.
Berecek Sean P.
Ding Zhu
Lemonovich John E.
Sharp William A.
Werner James C.
Ansaldo Sts Usa Inc.
Smart & Biggar
Union Switch & Signal Inc.
LandOfFree
Cab signal receiver demodulator employing redundant, diverse... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cab signal receiver demodulator employing redundant, diverse..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cab signal receiver demodulator employing redundant, diverse... will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1461122