Cache accessing method and apparatus

Details Cache accessing method and apparatus Cache accessing method and apparatus

G - Physics

06

F

354/239

G06F 12/10 (2006.01) G06F 12/02 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2008313

IMPROVED CACHE ACCESSING METHOD AND APPARATUS ABSTRACT OF THE INVENTION An addressable cache memory stores a plurality of lines of data from the main memory, and a tag memory (typically a part of the cache memory) stores a corresponding plurality of real addresses associated with each line of data. A cache accessing unit receives a virtual address from a CPU. The virtual address comprises a real address portion and a virtual address portion, and the virtual address portion includes a virtual page and segment address. On each cache access, the cache accessing unit initially addresses the cache memory by concatenating the real address portion of the virtual address with an algorithmically determined first real address (i.e., a real page address). A translation memory translates the virtual address portion of the virtual address into a second real address as the cache memory is being accessed. A comparator compares the second real address with the first real address, and the data is retrieved from the cache memory when the first real address matches the second real address. All subsequent cache accesses are made using a combined address formed by concatenating the real address portion of the current virtual address to the previously translated real page address. 12172-16/17

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