Cache and virtual memory organization

Details Cache and virtual memory organization Cache and virtual memory organization

G - Physics

06

F

354/239

G06F 12/08 (2006.01) G06F 12/10 (2006.01)

Patent

CA 1273715

ABSTRACT A cache-based computer architecture is disclosed in which the address generating unit and the tag comparator are packaged together and separately from the cache RAMs. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.

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