Cache controller

Details Cache controller Cache controller

G - Physics

06

F

G06F 13/12 (2006.01) G06F 9/38 (2006.01) G06F 13/14 (2006.01)

Patent

CA 2056174

A cache controller is coupled between a central processing unit (CPU) and a memory management unit (MMU). The MMU is coupled to main memory, and the cache controller is further coupled to a cache memory. A cache controller transfers a block of N programming instructions from the main memory into the cache memory. Once this transfer is complete, the CPU begins the sequential execution of the N instructions. Generally concurrently, the cache controller scans each of the N instructions to detect branch instructions. Branch instructions are those instructions which require additional data not found within the block of N instructions previously loaded into the cache. Upon detection a branch instruction, and prior to the execution of the branch instruction by the CPU, the cache controller fetches the branch instruction data from main memory, and stores it within the cache.

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