Cache disable for a data processor

Details Cache disable for a data processor Cache disable for a data processor

G - Physics

06

F

354/241

G06F 12/08 (2006.01) G06F 13/16 (2006.01)

Patent

CA 1233271

CACHE DISABLE FOR A DATA PROCESSOR Abstract A data processor is adapted for operation with a memory containing a plurality of items of operating information for the data processor. In addition a cache stores a selected number of all of the items of the operating information. When the cache provides an item of operating information, the memory is not requested to provide the item so that a user of the data processor cannot detect the request for the item. A disable circuit is provided to prevent the cache from providing the item when a signal external to the data processor is provided. Consequently, a user, with the external signal, can cause the data processor to make all of its requests for items of operating information to the memory where these requests can be detected.

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