Cache memory command circuit

Details Cache memory command circuit Cache memory command circuit

G - Physics

06

F

354/246

G06F 13/00 (2006.01) G06F 13/16 (2006.01)

Patent

CA 1116756

52E2720 ABSTRACT Apparatus and method for providing a buffer stage, or cache memory command circuit, between a cache memory unit and a main memory unit. The transfer of data between a main memory unit and a cache memory unit can be complicated because the circuits utilized in the cache memory unit and/or the main memory unit in effectuating the data transfer can be pre-empted. In addition, the data transfers must be executed in sequential order. According to the present invention, the transfer of data is divided into two portions, a portion involving cache memory unit and a portion involving the main memory unit along with associated interface units. The cache memory unit stores the data transfer commands and the associated data in sequential order. The cache memory unit and the main memory and interface units can execute their respective portions of the data transfer independently permitting overlapped instruction execution. The cache command buffer insures that the operations involving the two units of the data processing unit are executed in sequence. When data transfer has been completed, the cache command circuit continues to the execution of the next data transfer in sequence.

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